1) Technical field of the Invention
The present invention relates to a semiconductor memory device including two layers of bit lines formed thereon.
2) Description of Related Arts
Semiconductor memory devices used in the recent office automation equipments, for example, a personal computer and a word processor, demand the semiconductor memory devices capable of storing and reading larger amount of data. In order to meet this demand, a variety of approaches have been proposed up to the present. Among others, commonly assigned U.S. Pat. Nos. 5,280,441 and 5,379,820 both granted to Wada et al. disclose a circuit design with a T-shaped bit line for connection between the memory device and circuits arranged therearound, which decreases limitations on the circuit and allows the circuits to be arranged in a suitable manner around the memory device. Also, commonly assigned U.S. Pat. Nos. 5,563,820 and 5,699,308 both granted to Wada et al. teach an integrated semiconductor memory device, of which high density is achieved by appropriately adjusting intervals between the adjacent first-layer bit lines. The aforementioned U.S. patents are incorporated herein by reference in this patent application.
When the integration of MOSFETs formed beneath the first-layer bit line is greater than that of metal wire layers, it is expected that the dimensions of memory cell regions may be subject to those of the dimensions of the first-layer and second-layer bit lines.
In particular, when the through-hole acting as a connecting hole between the first-layer and second-layer bit lines is arranged on a memory cell region, the interval of adjacent first-layer bit lines are extended so that the dimension of the memory cell region should also be extended. Thus, the dimension of a memory cell arrays is extended, and the area thereof is increased. In other words, this causes the enlargement of the memory cell array, preventing the array from being highly integrated.
Details of prior arts and defects thereof are also described in the description of the Japanese Patent Application No. 11-347449, filed by the applicant.